circuit note cn- 0279 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more i nformation and/or support , visit www.analog.com/cn0279 . devices connected /referenced ad9642 14 - bit, 250 msps analog - to - digital converter ADL5565 6 ghz ultrahigh dynamic range differential amplifier high if sampling receiver front end with band - pass filter rev. 0 circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, inciden tal, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. evaluation and desig n support design and integration files schematics, layout files, bill of materials circuit function and benefits the circuit , shown in figure 1 , is a narrow , band - pass receiver front end based on the ADL5565 ultralow noise differential amplifier driver and the ad9642 14- bit, 250 msps analog - to - digital converter (adc) . the third - order , butterworth antialiasing filter is optimized based on the performance and interf ace requirements of the amplifier and adc . the total insertion loss due to the fil ter network and other components is only 5.8 db. the overall circuit has a bandwidth of 1 8 mhz with a pass - band flatness of 3 db . the signal - to - noise ratio ( snr ) and spurious - free dynamic range ( sfdr ) measured with a 127 mhz analog input are 7 1. 7 db fs and 9 2 d bc , respectively . the sampling frequency is 205 msps, thereby positioning the if input signal in the second nyquist zone between 102.5 mhz and 205 mhz. circuit description the circuit accepts a single - ended input and converts it to differential input using a wide bandwidth (3 ghz) mini - circuits tc2 - 1t 1:2 transformer. the 6 ghz ADL5565 differential amplifier has a d ifferential input impedance of 2 00 ? when operating at a gain of 6 db , and 1 00 ? when operating at a gain of 12 db. a gain option of 15.5 db is also available. the ADL5565 is an ideal driver for the ad9642 , and the fully different ial architecture through the band - pass filter and into the adc provides good high frequency common - mode rejection , as well as minimizes second - order distortion products. the ADL5565 provides a gain of 6 db or 12 db , depending on the input connection. in the circuit, a gain of 12 db was used to compensate for the insertion loss of the filter network and transformer (approximately 5 .8 db), provi di ng an overall signal gain of 5. 5 db. figure 1. 14 - bit, 250 msps wideband receiver fron t e nd (simplified schematic: all connections and decoupling not shown) gains, losses, and sig nal levels measured values for an input frequency of 127 mhz 0.1f 0.1f 0.1f 33pf 36nh 0.1f ADL5565 g = 12db 2.5pf xfmr 1:2 z tc2-1t input z = 50? z i = 100? internal input z ad9642 14-bit 205msps adc 620nh 5? 5? 187? 40? 217? +3.3v +1.8v drvdd +1.8v avdd 5.6db loss 0.2db loss 5.8db loss 11.8db gain fs = 1.75v p-p diff 620nh 0.5db loss analog input +1.5dbm fs at 127mhz overall gain = 5.5db 100? 100? 0.1f 5? 5? 15? 15? 2.85k? 1.2pf 1.2pf 33pf vcm 36nh vip2 vin2 vip1 vin1 10823-001
cn- 0279 circuit note rev. 0 | page 2 of 5 an input s i gnal of 1.5 dbm produces a full - scale 1.75 v p - p differential signal at the adc input. the anti aliasing filter is a third - order , butterworth filter designed with a standard filter design program. a butterworth filter was chosen because of its pass - band flatness . a third - order filter yields a n ac noise bandwidth ratio of 1.05 and can be designed with the aid of several free filter programs such as nuhertz technologies filter free, or the quite universal circuit simulator ( q ucs ) free simulation . t o achieve best performance, load the ADL5565 with a net differential load of 200 ?. the 15 ? series resistors isolate the filter capacitance from t he amplifier output, and the 100 ? resistors in parallel with the downstream impedance y ield a net load impedance o f 217 ? when added to the 30 ? series resistance. the 5 ? resistors in series with the adc inputs isolate internal switching transients from the f ilter and the amplifier. th e 2.85 k? input impedance was determined using the down - loadable spreadsheet on t he ad9642 webpage. simply use the parallel track mode values at the center of the if frequency of interest. the spreadsheet shows both the real and imaginary values. the third - order , butterworth filter was designed with a source impedance ( differential ) of 200 ?, a load impedance ( differential ) of 2 00 ?, a center frequency of 127 mhz, and a 3 db bandwidth of 20 mhz . the calculated values from a standard filter design program are shown in figure 1 . because of the high values of series inductance required, the 1.5 9 h inductors were decreased to 620 nh , and the 0. 987 p f capacitors increased proportionally to 2. 53 pf , thereby maintaining the same resonant frequency of 127 mhz , with more realistic component values. figure 2. starting design for third - order , differential butterworth filter with z s = 20 0 ?, z l = 200 ?, f c = 127 mhz , and bw = 20 mhz the internal 2 .5 pf capacitance of the adc was subtracted from the value of the second shunt cap acitor to yield a value of 37.3 pf. in the circuit, this capacitor was located near the adc to reduce/absorb the charge kickback. the values chosen for the final filter passive components ( after adjusting for actual circuit parasitics ) are shown in figure 1 . the measured performance of the system is summarized in table 1 , where the 3 db bandwidth , 18 mhz centered at 1 2 7 mhz . the total insertion loss of the network is approximately 5. 8 db. the frequency re spo nse is shown in figure 3 , and the snr and sfdr performance are shown in figure 4 . table 1 . measured performance of the circuit performance ec ification s at 1 d 1.7 v amle rate 20 mp inal results center frequency 127 mhz pass -b and flatness (11 8 mhz to 1 3 6 mhz ) 3 db snrfs at 127 mhz 71. 7 dbfs sfdr at 127 mhz 9 2 dbc h2 /h3 at 127 mhz 9 3 dbc / 9 2 dbc overall gain at 127 mhz 5. 5 db input drive at 127 mhz 0 .5 dbm (?1 dbfs) figure 3. pass- b and flatness performance vs . frequency figure 4. snr /sfdr performance vs. frequency , sample rate = 205 msps 39.8pf (2.53pf) 0.987pf (2.53pf) 0.987pf 39.5nh 39.8pf 100? 200? (620nh) 1.59h (620nh) 1.59h 100? + ? 39.5nh 10443-002 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 amplitude (dbfs) analog input frequenc y (mhz) 50 250 200 150 100 300 10823-003 50 55 60 65 70 75 80 85 90 95 1 18 120 122 124 126 128 130 132 134 136 snr (dbfs), sfdr (dbc) analog input frequenc y (mhz) snr (dbfs) sfd r ( db c) 10823-004
circuit note cn- 0279 rev. 0 | page 3 of 5 figure 5. general ized differential amplifier / adc interface with band - p ass filter filter and interface design procedure in this section , a general approach to the design of the amplifier/ adc interface with a band - pass filter is presented. t o achieve optimum performance (bandwidth, snr, and sfdr), there are certain design constraints placed on the general circuit by the amplifier and the adc . 1. the amplifier must see the correct dc load recommended by the data sheet for optimum performance. 2. the correct amount of series resistance must be used between the amplifier and the load presented by the filter. this is to prevent undesired peaking in the pass band . 3. the input to the adc must be reduced by external parallel resistor s , and the correct series resistance must be used to isolate the adc from the filter. this series resistor also reduces peaking. the generalized circuit shown in figure 5 applies to most high speed differential amplifier/adc interfaces and was used as a basis for the band - pass filter . this design approach tend s to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high speed adcs and the relatively low impedance of the driving source (amplifier). the basic design process is as follows: 1. set the external adc termination resistors, r tadc , so that the parallel combination of r tadc and r adc is between 200 ? and 400 ? . 2. select r kb based on experience and/or the adc data sheet recommendations, typically between 5 ? and 36 ?. 3. calculate the filter load impedance using z aafl = 2 r tadc || ( r adc + 2 r kb ) 4. select the amplifier external series resistor , r a . make r a less than 10 ? if the amplifier differential output impedance is 100 ? to 200 ?. make r a between 5 ? and 36 ? if the output impedance of the amplifier is 12 ? or less. 5. select z aafl so that the total load seen by the amplifier , z al , is optimum for the particular differential amplifier chosen using the following equation: z al = 2 r a + z aafl 6. calculate the filter source resistance by z aafs = z o + 2 r a 7. using a filter design program or tables design the filter using the source and load impedances, z aafs and z aafl , type of filter, bandwidth, and order. use a bandwidth that is about 10 % higher than the desired bandwidth of the application pass band to ensure flatness in the frequency span. after running these preliminary calculations, the circuit must be given a quick review for the following items . 1. the value of c aaf 3 must be at least 10 pf so that it is several times larger than c adc . this minimizes the sensitivity of the filter to variations in c adc . 2. the ratio of z aafl to z aafs must not be more than about 7 so that the filter is within the limits of most filter tables and design programs. 3. the value of c aaf1 must be at least 5 pf to minimize sensitiv ity to parasitic capacitance and component variations. 4. the inductor, l aaf , must be a reasonable value of at least several nh. 5. the value of c aff2 and l aaf1 must be reasonable values. sometimes circuit simulators can make these values too low or too high. t o make these values more reasonable, simply ratio these values with better standard value components that maintain the same resonant frequency. in some cases, the filter design program can provide more than one unique solution, especially with higher order filters. the solution that uses the most reasonable set of component values should always be chosen. also , choose a configuration that ends in a shunt capacitor so that it can be combined with the adc input capacitance. 0.1f 0.1f 0.1f c aaf1 c aaf2 c aaf2 l aaf l aaf1 l aaf1 l aaf 0.1f gain c adc xfmr 1:2 z input z = 50? internal input z adc internal input z z o /2 z o /2 z aafl z aafs z al avdd_amp drvdd avdd analog input z = r i /2 r tadc r tadc 0.1f r kb r kb r a r i r a r adc c aaf3 vcm 10823-005
cn- 0279 circuit note rev. 0 | page 4 of 5 circuit optimization techniques and trade - o ffs the parameters in this interface circuit are very interactive ; therefore , it is almost impossible to optimize the circuit for all key specifications (bandwidth, bandwidth flat ness, snr, sfdr, and gain) . however, the peaking , which often occurs in the bandwidth response , can be minimized by varying r a and r kb . the value of r a also affects snr performance. larger values, while reducing the bandwidth peaking, tend to slightly inc rease the snr because of the higher signal level required to drive the adc full scale . select t he r kb series resistor on the adc inputs to minimize distortion caused by any residual charge injection from the internal sampling capacitor within the adc. increasing this resistor also tends to reduce bandwidth peaking. however, increasing r kb increases signal attenuation, and the amplifier must drive a larger signal to fill the adc input range. for optimizing center frequency , pass - band characteristic s, t he series capacitor, c aaf2 , can be varied by a small amount. normally, t he adc input termination resistor, r tadc , is selected to make the net adc input impedance between 200 ? and 400 ? , which is typical of most amplifier characteristic load values . using too high or too low a value can have an adverse eff ect on the linearity of the amplifier. balancing these trade - offs can be somewhat difficult. in this design, each parameter was given equal weight ; therefore , the values chosen are represent ative of the interface performance for all the design characteristics. in some designs, dif ferent values can be chosen to optimize sfdr, snr , or input drive level, depending on system requirements. the sfdr performance in this design is determined by two factors : the amplif ier and adc interface component values , as shown in figure 1 . note that the signal in this design is ac - coupled with the 0.1 f capacitors to block the common - mode voltages between the amplifier, its termination resistors, and the adc inputs. r efer to the ad9642 data sheet for further details regarding common - mode voltages . passive component and pc board parasitic considerations the performance of this or any high speed circuit is highly dependent on proper printed circuit board ( pcb ) layout. this includes, but is not limited to, power supply bypassing, controlled impedance lines ( where required), component placement, signal routing, and power and ground planes. see tut or ia l mt - 031 and tut or ia l mt - 101 for more detailed informatio n regarding pcb layout for high speed adcs and amplifiers. in addition, see the cn - 0227 and the cn - 0238. use l ow parasitic surface - mount capacitors, inductors, and r esistors for the passive components in the filter. the inductors chosen are from the coilcraft 0603cs series . the surface - mount capacitors used in the filter are 5%, c0g, 0402 type for stability and accuracy . see the cn - 0279 design support package for the complete documentation on the system. c ommon variations the ad9643 is a dual version of the ad9642 . for lower power and bandwidth , the ada4950 - 1 and/or adl5561 / adl5562 can also be used. th ese device s are pin compatible with the other singles previously listed . circuit evaluation and t est t his circuit uses a modified ad9642 - 250ebz circuit board and the hsc - adc - e va l c z fpga - based data capture board . the two boards have mating high speed connectors, allowing for the quick setup and evaluation of the performance of the circuit . the modified ad9642 - 250ebz board contains the circuit evaluated as described in this note, and the hsc - adc - e va l c z data capture board is used in conjunction with visualanalog ? evaluation software , as well as the spi controller software to properly control the adc and capture the data. see u ser guide ug - 386 for the schematics, bom , and layout for the ad9642 - 250ebz board. the readme.txt file in the cn - 0279 design support package describes the modifications made to the standard ad9642 - 250ebz board. application note an - 835 contains complete details on how to set up the hardware and software to run the tests described in this circuit note .
circuit note cn- 0279 rev. 0 | page 5 of 5 learn more cn - 0279 design support package: http://www.analog.com/cn0279 - designsupport ug - 386 user guide, evaluating the ad9642/ad9634/ad6672 analog - to - digital converters arrants , alex, brad brannon and rob ree der, an - 835 application note , understanding high speed adc testing and evaluation , analog devices . ardizzoni, john. a practical guide to high - speed printed - circuit - board layout , analog dialogue 39 - 09, september 2005. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd , analog devices. mt - 101 tutorial, decoupling techniques , analog devices. quite universal circuit simulator nuhertz technologies, filter free filter design program reeder, rob , achieve cm con vergence between amps and adcs , electronic design, july 2010. reeder, rob, mine these high - speed adc layout nuggets for design gold , electronic design, september 15, 2011. rarely asked questions: considerations of high - speed converter pcb design, part 1: power and ground planes , november 2010. rarely asked questions: considerations of high - speed converter pcb design, part 2: using power an d ground planes to your advantage , february 2011 . r arely asked questions: considerations of high - speed conv erter pcb design, part 3: the e - pad low down , june 2011 . data sheets and evaluation boards ad9642 data sheet ADL5565 data sheet circuit evaluation board ( ad9642 - 250ebz) standard data capture platform ( hsc - adc - evalcz) revision history 7 /1 2 rev ision 0 : initial version (continued from first page) circuits from the lab circuits are intended onl y for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or other wise under a ny patents or other intellectual property by application or use of the circuits from the lab circuits. information furnished by analog devices is believed to be accurate and reliable. however, circuits from the lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability , noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for an y infringements of patents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do s o. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn10823 - 0 - 7/12(0)
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